1. Field of the Invention
The present invention generally relates to integrated circuits and more specifically to structures and methods for reducing gate induced drain leakage in semiconductor devices.
2. Description of the Related Art
As device geometries shrink, reliability problems due to gate induced drain leakage (GIDL) force the integrated circuit to operate at voltages which are lower than desired for best performance. Gate induced drain leakage results from the generation of electron-hole pairs in the surface the depletion region of a field effect transistor (FET) along the area where the gate conductor overlaps the drain diffusion region when the device is biased such that the drain potential is more positive (by greater than approximately 1V) than the gate potential.
As shown in FIG. 1 it is necessary for a portion of the drain diffusion region 10 to be positioned under the gate conductor 11. Therefore, if the gate conductor were at 0 V and the drain diffusion region 10 were at a positive voltage there would be a volume of carrier generation 12 due to the drain 10 to gate 11 electric field, which decreases device performance. In logic circuits, GIDL increases standby power. In a DRAM (dynamic randan access memory) array MOSFET (metal oxide semiconductor field effect transistor) GIDL degrades data retention time.
Furthermore, the GIDL problem is exacerbated when DRAM array MOSFETS are operated at negative wordline low levels or with an opposite gate doping polarity (i.e. P+ gated N-type field effect transistor (NFET)) because such operating parameters increase the potential between the drain and the gate conductor.
Therefore, there is a need to produce a structure which eliminates the gate induced drain leakage problem.